1. Field of the Invention
The present invention relates to thin-film transistor substrates which are applicable to liquid crystal displays and relates to liquid crystal displays provided therewith. In particular, the present invention relates to a structure of a terminal or pixel electrode which is composed of indium tin zinc oxide or indium zinc oxide.
2. Description of the Related Art
FIG. 29 is a schematic plan view of a thin-film transistor array substrate of a typical thin-film transistor liquid crystal display. The thin-film transistor substrate is provided with top-gate thin-film transistors, gate lines, source lines, and pixel electrodes. FIGS. 30 and 31 are partial cross-sectional views of the thin-film transistor array substrate.
In this thin-film transistor array substrate, gate lines G and source lines S are arranged in a matrix on a transparent substrate 100. Regions surrounded by the gate lines G and the source lines S constitute pixel regions. Each pixel region is provided with a pixel electrode 101.
An island of a semiconductor film 102 composed of n+ polysilicon or amorphous silicon is formed on the transparent substrate 100 at a corner of each pixel region. A gate insulating film 103 (refer to FIGS. 30 and 31) is formed so as to cover the semiconductor film 102 and the transparent substrate 100. The gate line G is formed on the gate insulating film 103 and a gate electrode 105 extends from the gate line G toward the center of the semiconductor film 102. A channel section 102a of the semiconductor film 102 opposes the gate electrode 105 and is separated therefrom by the gate insulating film 103.
An upper insulating film 106 is formed to cover the gate insulating film 103, the gate line G, and the gate electrode 105, and the source line S is formed on the upper insulating film 106. A source electrode 107 extends from the source line S and is connected to one end of the semiconductor film 102 via a contact hole 108 which is formed in the gate insulating film 103 and the upper insulating film 106. Another contact hole 109 is formed in the gate insulating film 103 and the upper insulating film 106 at the other end of the semiconductor film 102. A drain electrode 110 is formed on the upper insulating film 106 and is connected to the other end of the semiconductor film 102 via the contact hole 109.
A passivation film 111 composed of an insulating film is formed to cover the source electrode 107, the drain electrode 110, and the upper insulating film 106. The pixel electrode 101 is formed on the passivation film 111 and is connected to the drain electrode 110 via a contact hole 112 formed in the passivation film 111. A pad terminal 115 is formed on the passivation film 111 at one end of the source line S and is connected to the end of the source line S via a contact hole 113 formed in the passivation film 111. A thin-film transistor T6 is thereby formed as shown in FIG. 30.
Manufacturing steps of the top-gate thin-film transistor array substrate will now be described with reference to FIGS. 32 to 37.
A polysilicon semiconductor film and a SiO2 underlying insulating layer are deposited on the transparent substrate 100 of glass etc. These layers are patterned by a photolithographic process to form an island of semiconductor film 120 and underlying gate insulating film 121, as shown in FIG. 32.
Next, a gate insulating film and an electrode film for forming a gate electrode are deposited thereon, and are patterned by a photolithographic process to form a gate insulating film 122 and a gate electrode 123.
With reference to FIG. 34, both ends of the semiconductor film 120 are subjected to ion doping and are then covered with an insulating interlayer 125. Contact holes 126 and 127 are formed in the insulating interlayer 125 at the both ends of the semiconductor film 120. With reference to FIG. 35, a source electrode 128 is formed on the insulating interlayer 125 and is connected to one end of the semiconductor film 120 via the contact hole 126, whereas a drain electrode 129 is formed on the insulating interlayer 125 and is connected to the other end of the semiconductor film 120 via the contact hole 127.
With reference to FIG. 36, an insulating film is formed as a passivation film 130 thereon. A contact hole 131 reaching the source electrode 128 and a contact hole 132 reaching the drain electrode 129 are formed in the passivation film 130.
With reference to FIG. 37, an ITO (indium tin oxide) pixel electrode 133 is formed on the passivation film 130 and is connected to the drain electrode 129 via the contact hole 132, whereas an ITO terminal electrode 135 is formed on the passivation film 130 and is connected to the source electrode 128 via the contact hole 131. A top-gate thin-film transistor T7 is thereby formed. This top-gate thin-film transistor T7 has substantially the same structure as that of the thin-film transistor T6.
In the top-gate thin-film transistor T7 shown in FIG. 37, the contact holes 131 and 132 are formed in the passivation film 130 in order to connect the pixel electrode 133 to the drain electrode 129 and to connect the terminal electrode 135 to the source line S. Such a configuration requires a photolithographic process for forming the contact holes, including an exposure step, a dry etching step, a stripping step, and a cleaning step. The thin-film transistor T6 shown in FIGS. 29 to 31 also has the same problem.
The reason why the pixel electrode 133 is provided after forming the passivation film 130 will now be described.
If the ITO pixel electrode 133 is directly connected to the drain electrode 129 without forming the passivation film 130, the source electrode 128 and the drain electrode 129 must be immersed into an etching solution (HCl:HNO3:H2O=1:0.08:1) for etching the ITO during the photolithographic patterning step of the ITO pixel electrode 133. Thus, the source electrode 128 and the drain electrode 129 will also be undesirably etched by the etching solution.
In order to avoid such an undesirable etching, the source electrode 128 and the drain electrode 129 are covered with the passivation film 130, and the ITO transparent conductive film is formed and then patterned to form the pixel electrode 133 and the terminal electrode 135. That is, such a configuration unavoidably requires the passivation film 130 and thus requires a series of steps for forming and patterning the passivation film 130.